A volatile semiconductor memory device such as a Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM) may include a high voltage generating circuit. The high voltage generating circuit may be used, for example, during a wafer burn-in test, driving a word line in a DRAM in a normal operating mode, or compensating threshold voltage loss caused by an N-type MOS transistor. The burn-in test may be an accelerated test, which may apply, for a determined time, a voltage stress or temperature stress higher than normal environment operation conditions to a semiconductor memory device. Electrical characteristics of a semiconductor memory device may be evaluated after applying the stresses, thereby screening weak and/or bad cells.
To generate a voltage to drive a word line or a stress voltage, a high voltage VPP having a level higher than a normal power source voltage VDD may be required. A higher voltage may be generated by a high voltage generating circuit configured within a semiconductor memory device.
A high voltage generating circuit may be constructed of a ring oscillator, a charge pump, or a level detector. A level detector may compare a feed-back high voltage VPP with a reference voltage Ref, and may output a detection signal that provides a level increase or decrease of the high voltage VPP. A ring oscillator may generate pumping clocks CK,/CK corresponding to a detection signal output from the level detector. A charge pump may output a high voltage VPP traced to the reference voltage Ref through charge pumping operation responding to the pumping clocks.
FIG. 1 is a circuit diagram of a charge pump 11 in a high voltage generator of the prior art. FIG. 1 illustrates a circuit configuration of a cross-coupled charge pump, which may include two capacitors C1 and C2, four P-type MOS transistors P1-P4, and three N-type MOS transistors N1-N3. The charge pump may be used to obtain a split output characteristic in order to correct a duty ratio of clock signals. Such cross-coupled charge pump may be known as a boosting circuit of two inputs/outputs, and may be used as a duty detector within a duty compensation circuit (DCC) for clock signals. The cross-coupled charge pump may be known to have simple, reliable and/or high performing characteristics.
In the circuit illustrated in FIG. 1, a split of output voltage may increase when a duty of input clock signal is over 50%; and a split of output voltage may not increase when a duty of input clock signal approaches 50%. The reason why the split of output voltage is represented on both output terminals may be due to a difference of current flowing through both output terminals (out, outb) caused by stored charge amounts of pumping capacitors C1 and C2.
For a duty detector to perform a function, a split performance of the charge pump may become an important performance reference for a charge pump circuit, and the split performance may be limited by various error factors.
If a split is generated at both output terminals (out and outb) of the charge pump circuit, voltages for a load may become different, therefore, there may be a difference in drain-source voltages Vds of cross-coupled P-type MOS transistors P2 and P3. This may be provided by a current difference, and currents of output nodes become equal even though a duty of input signal is not 50%. In other words, if an output impedance is relatively low, output voltages of both output terminals may not split. Also, if an output impedance of output load is low, currents flowing through both output nodes may become equal and so a split of output voltage may be stopped. Thus, to increase the output impedance in the circuit of FIG. 1, a length of a gate of load transistors may have to be longer. The increase in the gate may cause a larger area to be occupied and may create integration limitations.
FIG. 2 is a graph illustrating a split characteristic of an output voltage based on a length of a gate. A transverse axis indicates time, and a longitudinal axis indicates voltage. Graphs G1 and G4 individually indicate split curves represented in both output terminals when a gate length of a load transistor is lengthened, and G2 and G3 individually provide split curves represented in both output terminals when a gate length of load transistor is relatively short. For example, when a signal having a duty of 49.5% is applied as a differential input to the circuit of FIG. 1, an output split of the charge pump becomes continuously wider as shown in the graphs G1 and G4 in the case that a load gate length may be relatively long, while in the case the gate length may be relatively short, the split may be stopped at a given time point as shown in the graphs G2 and G3. To increase an output impedance in the charge pump circuit of the prior art, a gate length of cross-coupled load transistor should be relatively long, but the length may cause a limitation in integration of semiconductor memory devices.